Teruo Tanimoto

Home

About me

CV (pdf)

Publications

Publications in Japanese

Recruitment

View My GitHub Profile

Publications

Conference Papers

  1. Yasunari Suzuki, Yosuke Ueno, Wang Liao, Masamitsu Tanaka, and Teruo Tanimoto,
    Circuit Designs for Practical-Scale Fault-Tolerant Quantum Computing,
    In Proceedings of Symposium on VLSI Technology and Circuits (VLSI ‘23), pp. 1-2, June 2023 (invited).
    (IEEEXplore)

  2. Wang LIAO, Yasunari Suzuki, Teruo Tanimoto, Yosuke Ueno, and Yuuki Tokunaga,
    WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code,
    In Proceedings of the 28th Asia and South Pacific Design Automation Conference (ASP-DAC ‘23), pp. 209-215, Jan. 2023.
    (acceptance rate: 102/328=31.1%)
    (IEEEXplore) (ACMDL)

  3. Satoshi Matsushita, Teruo Tanimoto, Satoshi Kawakami, Takatsugu Ono, and Koji Inoue,
    An Edge Autonomous Lamp Control with Camera Feedback,
    In Proceedings of the IEEE 8th World Forum on Internet of Things (WF-IoT ‘22), pp. 1-7, Oct.-Nov. 2022.
    (IEEEXplore)

  4. Yasunari Suzuki, Takanori Sugiyama, Tomochika Arai, Wang Liao, Koji Inoue, and Teruo Tanimoto,
    Q3DE: A fault-tolerant quantum computer architecture for multi-bit burst errors by cosmic rays,
    In Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture (MICRO-55), pp. 1110-1125, Oct. 2022.
    (acceptance rate: 83/366=22%)
    (IEEEXplore)

  5. Ilkwon Byun, Junpyo Kim, Dongmoon Min, Ikki Nagaoka, Kosuke Fukumitsu, Iori Ishikawa, Teruo Tanimoto, Masamitsu Tanaka, Koji Inoue, and Jangwoo Kim,
    XQsim: Modeling Cross-Technology Control Processors for 10+K Qubit Quantum Computers,
    In Proceedings of ACM/IEEE International Symposium on Computer Architecture (ISCA ‘22), pp. 366-382, June 2022.
    (ACMDL)

  6. Iori Ishikawa, Ikki Nagaoka, Ryota Kashima, Koki Ishida, Kosuke Fukumitsu, Keitaro Oka, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Akira Fujimaki, and Koji Inoue,
    Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device,
    In Proceedings of International Symposium on Circuits & Systems 2022 (ISCAS ‘22), pp. 3547-3551, May 2022.
    (IEEEXplore)

  7. Koki Ishida, Il-Kwon Byun, Ikki Nagaoka, Kosuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, and Koji Inoue,
    SuperNPU: Architecting an Extremely Fast Neural Processing Unit Using Superconducting Logic Devices,
    In Proceedings of the 53rd IEEE/ACM International Symposium on Microarchitecture (MICRO-53), pp. 58-72, Oct. 2020.
    (IEEEXplore)

  8. Koki Ishida, Masamitsu Tanaka, Ikki Nagaoka, Takatsugu Ono, Satoshi Kawakami, Teruo Tanimoto, Akira Fujimaki, and Koji Inoue
    32 GHz 6.5 mW Gate-Level-Pipelined 4-bit Processor using Superconductor Single-Flux-Quantum Logic,
    In Proceedings of the 2020 Symposia on VLSI Technology and Circuits, pp.1-2, June 2020.
    (IEEEXplore)

  9. Keitaro Oka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Koi Inoue,
    Enhancing a manycore-oriented compressed cache for GPGPU,
    In Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region (HPCAsia2020), pp.22-31, Jan. 2020.
    (ACMDL)

  10. Teruo Tanimoto, Takatsugu Ono, and Koji Inoue,
    CPCI Stack: Metric for Accurate Bottleneck Analysis on OoO Microprocessors,
    In Proceedings of the Fifth International Symposium on Computing and Networking (CANDAR ‘17), pp.166-172, Nov. 2017.
    (acceptance rate: 25/73=34.2%)
    (IEEEXplore)

  11. Hiroshi Sasaki, Fang-Hsiang Su, Teruo Tanimoto, and Simha Sethumadhavan,
    Why Do Programs Have Heavy Tails?,
    In Proceedings of the 2017 IEEE International Symposium on Workload Characterization (IISWC ‘17), pp.135-145, Oct. 2017.
    (acceptance rate: 23/83=27.7%)
    (IEEEXplore)

  12. Takatsugu Ono, Yotaro Konishi, Teruo Tanimoto, Noboru Iwamatsu, Takashi Miyoshi, and Jun Tanaka,
    FlexDAS: A Flexible Direct Attached Storage for I/O Intensive Applications,
    In Proceedings of IEEE International Conference on Big Data (IEEE BigData ‘14, accepted as a short paper), pp.147-152, Oct. 2014.
    (IEEEXplore)

  13. Hiroshi Sasaki, Teruo Tanimoto, Koji Inoue, and Hiroshi Nakamura,
    Scalability-based Manycore Partitioning,
    In Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques (PACT ‘12), pp.107-116, Sep. 2012.
    (acceptance rate: 39/207=18.8%)
    (IEEEXplore)

Workshop Papers

  1. Masamitsu Tanaka, Ikki Nagaoka, Satoshi Kawakami, Teruo Tanimoto, Takatugu Ono, Koji Inou, and Akira Fujimaki,
    High-Throughput Single-Flux-Quantum Circuits Based on Gate- Level-Pipelining toward Artificial Intelligence Applications,
    The Superconducting SFQ VLSI Workshop, Nov. 2022 (non-refereed).

  2. Teruo Tanimoto, Shuhei Matsuo, Satoshi Kawakami, Yutaka Tabuchi, Masao Hirokawa, and Koji Inoue,
    How many trials do we need for reliable NISQ computing?,
    In Proceedings of the First International Workshop on Quantum Computing: Circuits Systems Automation and Applications (QC-CSAA) in conjunction with ISVLSI 2020, pp. 288-290, July 2020.
    (IEEEXplore)

  3. Teruo Tanimoto, Shuhei Matsuo, Satoshi Kawakami, Yutaka Tabuchi, Masao Hirokawa, and Koji Inoue,
    Practical error modeling toward realistic NISQ simulation,
    In Proceedings of the First International Workshop on Quantum Computing: Circuits Systems Automation and Applications (QC-CSAA) in conjunction with ISVLSI 2020, pp. 291-293, July 2020.
    (IEEEXplore)

Journal Papers

  1. Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, and Hiroshi Nakamura,
    Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines,
    IEEE Computer Architecture Letters (Early Access), Oct. 2023.
    (IEEEXplore) (arXiv)

  2. Kuan Yi Ng, Aalaa M. A. Babai, Teruo Tanimoto, Satoshi Kawakami, and Koji Inoue,
    Empirical Power-Performance Analysis of Layer-wise CNN Inference on Single Board Computers,
    Journal of Information Processing, Vol.31, pp.478-494, Aug. 2023. (also printed in IPSJ Transactions on Advanced Computer Systems)
    (J-STAGE)

  3. Ikki Nagaoka, Ryota Kashima, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Taro Yamashita, Koji Inoue, and Akira Fujimaki,
    50-GFLOPS Floating-Point Adder and Multiplier Using Gate-Level-Pipelined Single-Flux-Quantum Logic with Frequency-Increased Clock Distribution,
    IEEE Transactions on Applied Superconductivity, vol. 33, no. 4, pp. 1-11, June 2023, Art no. 1302711.
    (IEEEXplore)

  4. Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kousuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, and Koji Inoue,
    Superconductor Computing for Neural Networks,
    IEEE Micro, vol.41, no.3, pp.19–26, May-June 2021.
    (IEEEXplore)

  5. Teruo Tanimoto, Takatsugu Ono, and Koji Inoue,
    Critical Path based Microarchitectural Bottleneck Analysis for Out-of-Order Execution,
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E102-A, No.6, pp.758-766, Jun. 2019.
    (J-STAGE)

  6. Teruo Tanimoto, Takatsugu Ono, and Koji Inoue,
    Dependence Graph Model for Accurate Critical Path Analysis on Out-of-Order Processors,
    IPSJ Journal of Information Processing, Vol.25, pp.983-992, Dec. 2017.
    (also printed in IPSJ Transactions on Advanced Computer Systems, Vol.10, No.3)
    (IPSJJIP) (IPSJACS)

  7. Teruo Tanimoto, Takatsugu Ono, Koji Inoue, and Hiroshi Sasaki,
    Enhanced Dependence Graph Model for Critical Path Analysis on Modern Out-of-Order Processors,
    IEEE Computer Architecture Letters, Vol.16, No.2, pp.111-114, July-Dec. 2017.
    (IEEEXplore)

  8. Hiroshi Sasaki, Fang-Hsiang Su, Teruo Tanimoto, and Simha Sethumadhavan,
    Heavy Tails in Program Structure,
    IEEE Computer Architecture Letters, Vol.16, No.1, pp.34-37, Jan.-June 2017.
    (IEEEXplore)

  9. Takatsugu Ono, Yotaro Konishi, Teruo Tanimoto, Noboru Iwamatsu, Takashi Miyoshi, and Jun Tanaka,
    A Flexible Direct Attached Storage for a Data Intensive Application,
    IEICE Transactions on Information and Systems, Vol.E98-D, No.12, pp.2168-2177, Dec. 2015.
    (J-STAGE)

Posters

  1. Koki Ishida, Masamitsu Tanaka, Ikki Nagaoka, Takatsugu Ono, Satoshi Kawakami, Teruo Tanimoto, Akira Fujimaki, Koji Inoue,
    Prototype Design of 32 GHz Microprocessor based on Superconducting Single-Flux-Quantum Logic,
    The International Conference for High Performance Computing (SC), Nov. 2019.

  2. Ghadeer Almusaddar, Teruo Tanimoto, Takatsugu Ono, Smruti Sarangi, Koji Inoue,
    Whitelisting Approach Using Hardware Performance Counters in IoT Microprocessors,
    4th Career Workshop for Women and Minorities in Computer Architecture, Oct. 2018.

  3. Teruo Tanimoto, Takatsugu Ono, Kohta Nakashima, and Takashi Miyoshi,
    Hardware-assisted Scalable Flow Control of Shared Receive Queue,
    In Proceedings of the 28th ACM International Conference on Supercomputing (ICS ‘14), p.175, Jun. 2014.
    (ACMDL)

Invited Talks

  1. Teruo Tanimoto,
    Research Activities toward Larger-Scale Cryogenic Quantum Computer Systems,
    Designers’ Forum in conjunction with ASP-DAC 2023, Jan. 2023.

  2. Teruo Tanimoto, Shuhei Matsuo, Satoshi Kawakami, Yutaka Tabuchi, Masao Hirokawa, and Koji Inoue,
    How can we exploit noisy intermediate-scale quantum computers? ~A computer architecture perspective~,
    The first workshop on Quantum and Classical Cryogenic Devices, Circuits, and Systems (QCCC 2019), Nov. 2019.

  3. Teruo Tanimoto, Takatsugu Ono, and Koji Inoue,
    Graph-based performance analysis on Out-of-Order processors,
    The seventh Asian Workshop on Smart Sensor Systems, Mar. 2019.

Awards

  1. APSCIT Computer Science and Informatics Research Contribution Award (2019), July 2019.

  2. Quick Report on Doctoral Theses Recommended by IPSJ SIGs (2017), May 2018. (The site is in Japanese.)

  3. IPSJ Computer Science Research Award for Young Scientists (2017), Nov. 2017. (The site is in Japanese.)

  4. IPSJ SIGARC Young Researcher Award (2016), Oct. 2016. (The site is in Japanese.)

Awards for my students

  1. Shuhei Matsuo, IPSJ SIGARC Young Researcher Award (2019), July 2019. (The site is in Japanese.)

Unpublished presentations

  1. Tesshu Nakamura, Makoto Miyamura, Koji Inoue, Satoshi Kawakami, Toshitsugu Sakamoto, Munehiro Tada, and Teruo Tanimoto,
    Dynamically Reconfigurable Decoder Architecture for Adaptive Error Correction Using Cryogenic Non-Volatile FPGAs,
    Workshop and Tutorial: I too can Quantum! (I2Q) in conjunction with ISCA 2023, June 2023.

  2. M.A. Babai Aalaa, Ng Kuan Yi, Tanimoto Teruo, Kawakami Satoshi, Inoue Koji,
    Non-Volatile FPGA-based Intermittent Computing and Its Performance Analysis,
    SIG Technical Reports, Vol.2022-ARC-250 No.14, pp.1-7, Oct. 2022.

  3. Kuan Yi Ng, Aalaa M.A. Babai, Satoshi Kawakami, Teruo Tanimoto, and Koji Inoue,
    Layer-wise power/performance analysis for single-board CNN inference,
    cross-disciplinary workshop on computing Systems, Infrastructures, and programminG (xSIG), July 2022.
    (Refereed but presented in a closed conference)

  4. Kuan Yi Ng, Aalaa M.A. Babai, Satoshi Kawakami, Teruo Tanimoto, and Koji Inoue,
    Layer-wise power/performance modelling for single-board CNN inference, SIG Technical Reports, Vol.2022-ARC-248 No.13, pp.1-11, Mar. 2022.